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An integrated circuit having a serial connection of memory cells comprises at least a first memory cell and a second memory cell. A first storage node of the first memory cell is connected to a first bit line through a first path, and a second storage node of the first memory cell is connected to a second bit line through a second path. A first storage node of the second memory cell is connected to the first storage node of the first memory cell through a first path, and a second storage node of the second memory cell is connected to the second storage node of the first memory cell through a second path. The first path and the second path are in a common metal layer.
The first and second paths have at least two circuit portions. A first circuit portion is a capacitance be359ba680
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